1. Field of the Invention
The present invention relates to a device under test (DUT) array for identifying defects and its operating method, and particularly to a DUT array having a plurality of test units arranged in a matrix.
2. Description of the Prior Art
Wafers should continuously undergo tests during manufacturing to maintain the quality of the products. At present, wafer acceptance testing (WAT) is one of the popular test structures. It provides a plurality of test keys in the scribe line area to monitor a variety of defects in the semiconductor processes. As the semiconductor processes are performed to fabricate devices or elements of integrated circuits, a plurality of test structures are simultaneously formed in the scribe line area utilizing the same processes to simulate those devices or elements respectively. Each of the mentioned test structures usually includes two input/output pads. The defects in the integrated circuits therefore can be detected by utilizing probes of the probe card to contact the input/output pads of the test keys over and over. The testing results gain from the probe card for those test structures are important indexes used to indicate the reliability of products.
To identify defects using these test structures, an input signal is provided on one end of the structure and it is determined if an appropriate output signal was generated at the other end. Test structures allow for the testing of “opens” and “shorts”. An open is a failure in the connectivity or an excessively high resistance between two allegedly connected points. An open-detecting pattern is typically used to detect opens. A short is a failure when connectivity exists between allegedly unconnected points. An open can be in a metal line, a polysilicon line, a diffusion line, a contact, or a via. A short can be metal-to-metal, polysilicon-to-polysilicon, diffusion-to-diffusion, or contact-to-polysilicon. A short-detecting pattern is typically used to detect shorts.
The above-referenced test structures, i.e. the open-detecting pattern and the short-detecting pattern, have distinct drawbacks. For example, locating and analyzing failures using either structure is difficult and time consuming. Specifically, detecting an open or short condition tells the user nothing about exactly where the defect is located. In addition, the input/output pads of the test structures usually occupy a large area in the wafer, because each input/output pad should be big enough for contacting with probes of the probe card. Since each test structure has two input/output pads, the test structure occupies a large area in the wafer.
Determining the location of the defect requires an inspection or a comparison of the structure by the user. In the current art, visual inspection is a major method of determining chip failure. A visual inspection is a tedious process, which requires considerable time of an experienced product engineer. Moreover, to complicate matters, not all visual defects result in electrical failures. Therefore, to more closely analyze the visual defects, the user must typically perform both optical and scanning electron microscope (SEM) examinations. Furthermore, many defects are not visible by initial inspection, thereby making localization of the defects with an SEM extremely difficult.
Therefore, a need arises for a cost-effective method and test structure to quantify the magnitude of and localize defects on a wafer.